SAN JOSE, Calif., July 22, 2021 – Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the delivery of Cadence Cerebrus Intelligent Chip Explorer, a new machine learning (ML) -based tool that automates and enables to scale the digital chip design, enabling customers to effectively achieve demanding chip design goals. The combination of Cerebrus and the Cadence RTL Approval Workflow gives advanced chip designers, CAD teams and IP developers the ability to improve engineering productivity up to 10x compared to a manual approach while achieving up to 20% power, performance and area (PPA).
With the addition of Cerebrus to the larger digital product portfolio, Cadence offers an advanced comprehensive ML-enabled digital workflow from synthesis to implementation and approval. The new tool is cloud-ready and uses highly scalable compute resources from leading cloud providers to quickly meet design requirements across a wide range of markets, including consumer, large-scale computing, 5G communications, automotive and mobile. For more information on Cerebrus, please visit www.cadence.com/go/cerebruspr.
Cerebrus offers customers the following benefits:
- ML Empowerment: Quickly find workflow solutions that human engineers might not naturally try or explore, improving PPA and productivity.
- ML Model Reuse: Automatically apply design learnings to future designs, reducing the time required to achieve better results.
- Improved Productivity: Allows a single engineer to automatically optimize the entire RTL to GDS stream for many blocks simultaneously, allowing entire design teams to be more productive.
- Massively Distributed Computing: Provides scalable design exploration on premise or in the cloud for faster workflow optimization.
- Easy to use interface: A powerful user cockpit enables interactive analysis of results and management of runs to gain valuable insight into design metrics.
âPreviously, design teams did not have an automated way to reuse historical design knowledge, resulting in excessive time spent on manual relearning with each new project and wasted margins,â said Dr. Chin-Chi Teng , senior and general vice president responsible for the Digital & Signoff group at Cadence. âThe delivery of Cerebrus marks a revolution in the EDA industry with ML-driven digital chip design where engineering teams have a greater opportunity to have greater impact in their organizations as they can offload manual processes. . As the industry continues to evolve into advanced nodes and the size and complexity of design increases, Cerebrus enables designers to achieve PPA goals much more efficiently.
Cerebrus is part of the complete Cadence digital flow, working seamlessly with the Genus Synthesis solution, the Innovus implementation system, the Tempus Timing Signoff solution, the Joules RTL Power solution, the Voltus IC Power Integrity solution and the verification system. Pegasus to provide customers with a quick path to design closure and better predictability. The new tool and the larger flow support the company’s intelligent systems design strategy, which enables ubiquitous intelligence for design excellence.
Cadence is a pivotal leader in electronics design, drawing on over 30 years of computer software expertise. The company applies its underlying intelligent systems design strategy to deliver software, hardware, and IP properties that turn design concepts into reality. Cadence customers are the most innovative companies in the world, providing extraordinary electronic products, from chips to boards to systems for the most dynamic applications in the market, including consumer computing, large-scale computing. , 5G communications, automotive, mobile telephony, aerospace, industry and health. For seven years in a row, Fortune magazine has named Cadence one of the Top 100 Companies to Work For. Learn more about cadence.com.